Floating plate capacitor with extremely wide band low impedance

ABSTRACT

A capacitor having a floating plate-shaped electrode, at least two patterned plate electrodes overlying the floating plate-shaped electrode, and a dielectric layer therebetween. The resulting structure exhibits high two-part insertion loss even at frequencies as high as 10 GHz. Notably, the capacitor exhibits an insertion loss of more than −40 dB over a range from 1 GHz to 10 GHz.

BACKGROUND OF THE INVENTION

[0001] The present invention is directed to parallel plate capacitors aswell as decoupling capacitors for semiconductor applications. Morespecifically, the invention is directed to discrete, low inductancecapacitors typically used in decoupling applications.

[0002] The purpose of power distribution systems is to deliver stable,noise-free power to integrated circuits (ICs) and other devices. One wayto express this quantitatively is that the power distribution impedance,as seen from a chip, must be less than some value, over whateverfrequency range is of interest. The value is determined by the voltagedrop or noise tolerance of the chip when it is drawing maximum current.For example, simply considering the DC drop allowed for a chip drawing 5A from a 5 V supply with a 5% voltage tolerance, the total powerdistribution impedance seen by the chip must be less than 50 mΩ. For ACnoise, time domain equivalent circuit simulations are usually performed,since a wide range of frequencies is generated by digital circuitry.Simultaneous switching drivers generate di/dt noise, as has beenexhaustively described elsewhere by H. B. Bakoglu, Circuits,Interconnections, and Packaging for VLSI, Chapter 7, Addison-Wesley,1990, incorporated herein by reference.

[0003] Capacitors have been used for decoupling, or bypassing AC noiseon DC power supply circuits for many years. These capacitors can bethought of as supplying localized energy storage for the varying currentdemands of circuitry, typically semiconductor circuits, and thusstabilizing the DC power.

[0004] At low frequencies, almost all capacitors are effective todecouple AC signals. Usually several capacitors are used on a printedcircuit board to provide a very low impedance path for AC signals, whilemaintaining DC isolation. For example, tantalum electrolytic capacitorsof 10 to 100 μF might be used to provide maximum energy storage and lowfrequency decoupling for an entire circuit board, while ceramic chipcapacitors of 0.1 μF might be located next to every integrated circuitto provide a local path for grounding high frequency noise.

[0005] Such distributed capacitance schemes worked well when the clockfrequencies of digital systems were relatively low, such as 10 to 20MHz. However, as clock frequencies have increased to above 100 MHz,conventional capacitors are limited. The problem is that in reality,capacitors also exhibit inductance and resistance components, and thisinductance becomes a problem at higher frequencies.

[0006] In that regard, a capacitor can be modeled as a series RLCcircuit. The inductance is present because of the finite dimensions ofthe plates and the way in which the plates are connected to theremainder of a circuit, the later exerting a major influence at thehigher frequencies. The limited dimensions of the conductors connectingthe plates to the remainder of the circuit impart finite, though small,inductances. Even in capacitors of moderate sizes, the resultinginductance-capacitance (LC) combination can resonate at a fairly lowfrequency. For example, the typical 0.1 μF ceramic chip capacitor(measuring 0.12 inch by 0.06 inch) has a self-inductance ofapproximately 500 pH and is self resonant around 20 MHz. From DC toaround 20 MHz, the impedance decreases down to a level of 150 mOhms, butabove 20 MHz, the impedance increases, and the capacitor loses itsdecoupling effectiveness. Stated in these terms, the capacitor can bethought of as a four terminal device, whose function is to prevent ACdisturbance imposed on one set of terminals from being coupled to theother set of terminals. In microwave terms, this two port network musthave a high insertion loss (S₁₂)between the two ports, to be effective.

[0007] Also detrimental to effective decoupling is the inductancebetween the IC (integrated circuit) chip itself and the printed circuitwiring board power distribution planes to which the decouplingcapacitors are connected. This inductance arises from the leads of thechip package. Connecting many leads in parallel to power and groundconnections does not totally eliminate this effect.

[0008] If large current swings are required by the IC circuitry, thisresidual inductance can cause unacceptable voltage drops and AC noise.To counteract this effect, decoupling capacitors have been included inIC circuit packages, often as discrete chip components, but sometimes asmultiple planes with thin dielectric layers between them, which ineffect form integral capacitors. This latter arrangement is particularlyeffective in multilayer ceramic packages such as pin grid arrays (PGAs),quad flat packs (QFPs) and ball grid arrays (BGAs).

[0009] In multichip modules (MCMs), the effect of the inductances ofchip-to-substrate interconnections can be minimized by using multipleinterconnections and careful design both in a wirebond and in a flipchip environment. Similarly, the intrinsic inductance and resistance ofpower distribution planes, either solid, perforated, or the new IMPS(interconnected mesh power system), is extremely low, and does notdetermine the effectiveness of power distribution. My prior U.S. Pat.No. 5,410,107 describes the IMPS.

[0010] Thus discrete decoupling capacitors are critical elements forreducing power distribution noise.

[0011] In MCM applications, there are three inductances to consider:interconnects between chip and substrate, substrate power and groundplanes, and the inductance of the capacitor itself, including itsconnection to the power and ground planes.

[0012] It has long been known that the least inductive capacitor is aparallel plate capacitor with a large area. The ultimate low-inductancecapacitor in MCM substrates is the parallel plate capacitor consistingof a thin layer of high dielectric constant material sandwiched betweenpower and ground planes. However, these capacitors are expensive tofabricate and contribute significantly to substrate defects. The need todistribute multiple voltages (e.g., 3.3 V, 5 V, etc.) makes their useprohibitive in many applications.

[0013] In an earlier patent of mine, U.S. Pat. No. 4,675,717, there isdescribed such a capacitor in the context of a wafer-scale integrated(WSI) assembly, built on silicon substrates, in which the conductivesilicon substrate forms the ground plate of the capacitor and allows theeasy growth of a silicon dioxide dielectric layer. A metal layer formedover the dielectric layer serves as the other plate of the capacitor, inaddition to serving as the power distribution plane. Such integratedpower distribution and decoupling capacitor combinations havedemonstrated low impedance characteristics without inductive resonancesto tens of gigahertz. But again, such structures are expensive toproduce, and do not work with many sets of packaging materials. Discretecapacitors are still required to handle the vast majority of decouplingapplications.

[0014] Various manufacturers have made progress on reducing theinductance of discrete capacitors.

[0015] One such manufacturer, AVX Corporation, produces low-inductancecapacitor arrays, designed in conjunction with IBM, in which multipleconnections to the plates are made along one side of the unit or part,using solder bumps or thermocompression gold ball bonding. See, J.Galvagni, “Low Inductance Capacitors For Digital Computers,” AVXTechnical Information brochure, and AVX Corporation product brochureentitled “Low Inductance Capacitor Arrays,” incorporated herein byreference. Such capacitors are made available under the designation AVXLICA—Low Inductance Decoupling Capacitor Arrays as an extension to IBMCorp.'s DCAP® decoupling capacitors. The AVX LICA are available invalues from 30 to 150 nF. Custom designs incorporating multiple sectionscan be produced. Testing of these devices results in measurements oftotal inductance below 60 pH.

[0016] Another manufacturer, Murata, produces a very small capacitor(20×20×13 mil) having a capacitance of 10 or 2.2 nF. The contacts are onopposite 20 mil square faces. Though originally designed to be mountedwith one face down and the other face wirebonded, it is possible toobtain even lower inductance by mounting the part with both terminalsperpendicular to the plane of a substrate.

[0017] H. Hashimi and P. Sandborn have described what is referred to asa close attached capacitor (CAC) which is a unit that is mounteddirectly on the active area of an IC chip, and wirebonded to chip powerand ground pads, to overcome inductance in the unit. See, H. Hashemi &P. Sandborn, “The Close Attached Capacitor: A solution to SwitchingNoise Problems,” Proceedings of the 42 nd ECTC, 1992, pp. 573-582,incorporated herein by reference. Unfortunately, the wirebondconnections are still significantly inductive, and the silicon-basedcapacitors are expensive.

[0018] Along other lines, there has been under development an integratedcapacitor layer for printed wiring boards to simultaneously create manycapacitors for radio frequency (RF) circuit applications as areplacement for discrete chip components. This layer uses patternedmetal as a set of floating plates underneath an unpatterned depositeddielectric, above which a set of patterned metal plates includingterminal pads is formed.

SUMMARY OF THE INVENTION

[0019] The present invention provides a new and novel capacitorstructure and method for making same. The capacitor comprises anextremely low inductance floating plate capacitor which can befabricated with as little as one patterning step. These devices can befabricated in large quantity on sheet or roll material and subsequentlyexcised by cutting or stamping.

[0020] These capacitors preferably are used in decoupling applications,which applications can advantageously utilize the low-inductance natureof the floating plate capacitor and its method of attachement. Theextremely high insertion loss, i.e., decoupling effectiveness of thesecapacitors is maintained at frequencies exceeding 1 GHz, even over awide band from about 1 GHz to 10 GHz.

[0021] In an embodiment, the invention provides a capacitor which doesnot exhibit a significant increase in impedance with increasingfrequency after exhibiting an inductive resonance.

[0022] In an embodiment, the invention provides a capacitor whichexhibits an average insertion loss of at least −40 dB at frequenciesabove 1 GHz.

[0023] In an embodiment, the invention provides a capacitor comprising afloating plate electrode, at least two patterned plate electrodesoverlying the floating plate electrode, and a dielectric layertherebetween.

[0024] In an embodiment, the capacitor is effective to exhibit aninsertion loss of at least −40 dB at frequencies from 1 to about 10 GHz.

[0025] In an embodiment, the floating plate electrode consists of ametal film (preferably aluminum or Ti-Cu) with a thickness of about 1000Å to about 1 μm.

[0026] In an embodiment, the dielectric layer is selected from the groupconsisting of barium titanate, tantalum oxide, aluminum oxide, organicdielectrics and inorganic dielectrics.

[0027] In an embodiment, the dielectric layer is from about 2000 Å toabout 1 μm thick.

[0028] In an embodiment, the at least two patterned plate electrodes areselected from the group consisting of metals, conductive inks andconductive pastes.

[0029] In an embodiment, the patterned plates comprise electroforms.

[0030] In an embodiment the invention provides an insulating layer on aface of the floating plate electrode opposite the at least two patternedplate electrodes.

[0031] In an embodiment, the insulating substrate is selected from thegroup consisting of oxidized metal, ceramic, silicon, glass and polymer.

[0032] In an embodiment, the invention provides a method of forming acapacitor comprising the steps of:

[0033] a) forming a floating plate electrode;

[0034] b) forming a dielectric layer over the floating plate electrode;and

[0035] c) forming at least two patterned plate electrodes on thedielectric layer in overlying relationship with respect to the floatingplate electrode.

[0036] In an embodiment the invention provides a method of forming acapacitor comprising the steps of

[0037] a) providing a metallic layer;

[0038] b) providing a dielectric layer on one face of the metalliclayer; and

[0039] c) providing at least one pair of patterned electrodes on thedielectric layer on a side of the dielectric layer opposite the metalliclayer.

[0040] In an embodiment, the invention further provides the step ofproviding an insulating layer on a face of the metallic layer oppositethe dielectric layer.

[0041] In an embodiment, the step of providing the metallic layer withan insulating layer comprises providing a metallic layer and thenoxidizing one side of the metallic layer until a sufficientlyelectrically insulating layer is formed.

[0042] In an embodiment, the metallic layer is aluminum.

[0043] In an embodiment, the metallic layer is a sheet of aluminum foil.

[0044] In an embodiment, the dielectric layer comprises barium titanate,tantalum oxide, aluminum oxide, an organic dielectric or an inorganicdielectric.

[0045] In an embodiment, the step of providing the patterned plates cancomprise sputtering plates onto the dielectric layer,photolithographically defining a metal, such as copper, onto thedielectric layer, screen printing a conductive ink or paste onto thedielectric layer, or electroplating an electroform in the dielectriclayer.

[0046] In an embodiment, the step of providing the metallic layercomprises providing a rollform metallic material.

[0047] In an embodiment, the step of providing an insulating layercomprises applying an insulating layer to the rollform metallicmaterial, e.g., by lamination, oxidation or other suitable application.

[0048] In an embodiment, a polymer sheet is coated with a metallic layerto provide the insulating layer and metallic layer, respectively.

[0049] These and other features and aspects of the invention arepresented below with reference to the drawings in the following detaileddescription of the presently preferred embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

[0050]FIG. 1 illustrates a cross sectional view of a capacitor embodyingprinciples of the invention.

[0051]FIG. 2 illustrates a plan view of the capacitor of FIG. 1.

[0052]FIG. 3 illustrates a plan view of a capacitor with multiple setsof patterned plates.

[0053]FIG. 4 illustrates a plan view of a BGA package including acapacitor embodying principles of the invention.

[0054]FIG. 5 illustrates a cross sectional view of the BGA packageincluding a capacitor embodying principles of the invention of FIG. 4.

[0055]FIG. 6 illustrates a testing arrangement by means of which theresults illustrated in FIG. 7 were produced.

[0056]FIG. 7 illustrates insertion loss curves, over a frequency rangefrom 0 to 20 GHz, for various prior art capacitors and a capacitorembodying principles of the invention.

[0057]FIG. 8 illustrates an insertion loss curve from 0 to 10 GHz for acapacitor embodying principles of the invention, with measurements madea different connection point.

[0058]FIG. 9 illustrates insertion loss curves over a frequency rangefrom 0 to 10 GHz for a 35 nF capacitor embodying principles of theinvention and a 55 nF AVX capacitor.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS

[0059] As described above, the present invention provides discretefloating plate capacitors, manufactured with as little as one patterningstep, preferrably for decoupling applications which can utilize thelow-inductance nature of the inventive capacitors to advantage.

[0060] A floating plate capacitor 10 embodying principles of theinvention is illustrated in FIGS. 1 and 2. There it can be seen that thefloating plate capacitor 10 basically comprises two parallel platecapacitors 12 and 14 positioned side-by-side. The capacitors 12 and 14have a common floating plate 16 supported on an insulating substrate 18,and separate patterned plates 20 and 22 positioned side-by-side above aninterceding dielectric layer 24. Connections to the capacitor 10 aremade via optional terminal pads 26 formed on the plates 20 and 22, asillustrated in FIG. 2.

[0061] It will be appreciated that if the total area of the twocapacitors 12 and 14 is A, there are effectively two capacitorsconnected in series, each having an area A/2. Thus, whatever capacitanceC would be formed in area A/2, the resulting capacitance of the seriesconnection of the capacitor pair is C/2. Since the capacitance of asingle parallel plate capacitor of area A would be 2C, it is clear thatthe floating plate capacitor 10 can only produce one-fourth of thecapacitance of a parallel plate capacitor of the same area.

[0062] However, a floating plate capacitor of the invention isadvantageous in that both of its terminals appear on the same side ofthe capacitor, to wit, the patterned plates 20 and 22. This creates aneconomy of manufacture and an extremely low inductance connection tocircuitry external to the capacitor, such as a planar power distributionnetwork.

[0063] With continued reference to FIGS. 1 and 2, a fabrication sequenceof the capacitor 10 will be explained.

[0064] As shown in FIG. 1, the fabrication sequence can begin with alarge sheet of insulating material, such as ceramic, silicon, glass orpolymer (including polymides), which then becomes the insulatingsubstrate 18. A thin layer of a metal, such as aluminum, is applied toone side by sputtering, evaporation, or lamination, to form what willbecome the common floating plate 16. The layer 16 could be as thin as1000 to 2000 Å and still provide sufficient low resistance, althoughlarger capacitors may require a thickness of 1-2 μm.

[0065] Next, a barrier layer, such as barium titanate, tantalum oxide,aluminum oxide, or other inorganic or organic dielectric is applied byappropiate means, such as sputtering, thereby to form the dielectriclayer 24. This layer 24 might typically be 2000 Å to 1 μm thick.

[0066] Next, one or more sets of patterned plates 18 and 20 are createdon top of the dielectric 24. These plates 18 and 20 could consist ofsputtered plates, photolith-ograpically defined areas of copper or othermetals, screen printed areas of conductive inks or pastes such as areused in polymer thick film circuitry, or electroplated forms. Optionalcapacitor terminal pads 26 are then provided on the plates 18 and 20, asnecessary. An optional insulating covercoat could be similarly applied,leaving exposed only the sets of capacitor terminal pads 26, but in manycases this covercoat would be unnecessary.

[0067] Finally, the resulting large sheet-like structure would be sawn,die cut or stamped into individual capacitors 10, as appropriate in thecircumstances.

[0068] Alternatively, the fabrication process could be performed inreel-to-reel fashion on polymer film. In such a process, the capacitorsare formed on a continuous ribbon of polymer film that can be wound fromone supply reel to another take-up reel. The polymer film could serve asthe insulating substrate 18.

[0069] Yet another alternative fabrication process could be performedwherein a metal sheet or foil, such as aluminum, is used to form thefloating plate of the one or more capacitors. The metal sheet could alsobe provided in a roll form, e.g., in reel to reel form. The metal couldbe anodized to form the dielectric layer by known chemical processes,thus eliminating any vacuum processing steps. Of course, the dielectriclayer could be provided by any other process described above. Aninsulating layer could be applied to the back of the processed metallayer or formed by oxidizing the back of the metal layer before or afterthe formation of the dielectric layer, or the metal layer could belaminated to a supporting insulator, such as FR-4 board before or afterthe formation of the dielectric layer. Thereafter, the patterned plateswould be formed on the dielectric layer according to any of the methodsset forth above (e.g., electroplated, photolithographically formed, madeof pastes or inks, et cetera).

[0070] In any event, the resulting structure would have or hasinherently low inductance, as would or do the interconnections. Forexample, the plates 18 and 20 could be attached to a power distributionsystem at many points with conductive epoxy or solder, with eachconnection exhibiting an inductance of less than 50 pH. If dictated bythe geometry of the interconnects, the two floating plates 18 and 20could be broken up into smaller plates, as illustrated in FIG. 3, withsome used for each polarity, with little increase in inductance.

[0071] It can be appreciated that in any of the foregoing fabricationprocesses, any need to pattern the dielectric layer is eliminated. Notpatterning the dielectric layer removes the concern of having to usehydrofluoric acid (HF), or other environmentally dangerous manufacturingprocess.

[0072] Versions of the above described capacitors could be mounted on ICchips designed to accomodate them. In such a case, the capacitors wouldfit inside the wirebond I/O frame and provide low inductance energystorage and power distribution noise reduction. Instead of beingwirebonded, as in Hashemi's and Sandborn's scheme, the capacitors couldbe epoxy attached to pads on the chip, with far lower inductance.

[0073] A particularly appealing application for the capacitors is as areplacement for the lid on PGA, BGA or QFP packages, as illustrated inFIGS. 3, 4 and 5. In FIGS. 3, 4 and 5, one such capacitor 30 is shown ina BGA package application 32. As can be seen, in this application, theconventional metal lid would be replaced by an appropiate rigid floatingplate planar capacitor 30. In this embodiment, the capacitor 30 has twosets of patterned plates (i.e., four total) 34 a-34 d. This is bestshown in FIG. 3.

[0074] As the cross sectional view in FIG. 5 shows, the typical BGApackage already has three cavity levels: die attach surface 40, wirebondshelf 42, and lid attach shelf 44. In the top view illustrated in FIG.4, long connection pads 36 a-36 d located about edge 38, which areconnected to power and ground planes(not illustrated) are provided onthe lid attach shelf 44.

[0075] It can be appreciated that the configuration shown is for fourpatterned plates 34 a-34 d on the capacitor 30, in order to distributethe power and ground connnections more evenly. These patterned plates 34a-34 d mate with the connection pads 36 a-36 d, respectively, viaconnection points 50 visible in FIG. 3. The connection would be bysuitable quantities and deposits of anisotropic adhesive,conducive/non-conductive preform, or dispensed sections of conductiveand non-conductive epoxy. In any event, conductive contact would existbetween the connection pads 36 a-36 d and the plates 34 a-34 d, and notover the portions of the lid attach shelf 44 separating the connectionpads 36 a-36 d.

[0076] As the capacitor 30 is inside the package cavity, no overcoatwould be required. Since multiple vias would be provided from thecapacitor attach pads 36 a-36 d to the internal power and ground planes,extremely low inductance connections would result.

[0077] As mentioned above, even the best currently available lowinductance chip capacitors of several nF are ineffective above severalhundred MHz. That is to say, these capacitors exhibit excessiveinductance above several hundred MHz, and thus are not suitable forapplications above that range. In contrast, current indications are thatcapacitors embodying the principles of the invention could provide morethan 50 nF effective to several tens of GHz.

[0078] In FIG. 6 there is illustrated a testing arrangement 100 utilizedto produce the results illustrated in FIG. 7. As can be seen, in thetesting arrangement, the capacitors were tested as two port networks, asis typical in microwave device testing.

[0079] In the testing arrangement 100, a capacitor 108 is tested byapplying a variable frequency power source 102 across one side of thepatterned plates 110 and 112 of the capacitor 108, with a small 50 ohmresistor 104 appropriately positioned in series to provide a load.Coupled across the opposite side of the patterned plates 110 and 112 ofthe capacitor 108 is a suitable voltage measuring device 106.

[0080] In FIG. 7 there is illustrated the result the measurement ofinsertion loss characteristics, over a wide frequency band, of severalprior art capacitors mentioned above, as well as a capacitor embodyingprinciples of the invention. The capacitors were a conventional ceramicchip capacitor of 10 nF, a Murata low inductance capacitor of 10 nF, anAVX LICA of 55 nF, and a capacitor embodying principles of theinvention. In Table 1, below, the results of other measurements on priorart capacitors is presented.

[0081] For these measurements, capacitors were measured using an HP4291A RF Impedance/Material Analyzer with low impedance probe head, anAlessi RM-06 probe station, and Cascade probe. For capacitors measuredas in FIG. 7, an HP 8510B network analyzer was used with GS and SGprobes. Each system was calibrated at the probe tips with a TektronixCAL93 calibration substrate. The probe has two terminals on a fine 150μm (6 mil) pitch.

[0082] In order to connect to the fine pitch probe, and to avoidintroducing additional parasitic inductions from interconnections, anovel probing technique was devised. In this technique, the capacitorswere mounted on a glass plate with non-conductive epoxy, and thenconductive epoxy was used to extend the terminals to the center of thetop surface of the capacitor body. The epoxy, after application with afine wire and curing, was polished by burnishing with a piece ofalumina. The epoxy was extended over the entire top surface of thecapacitor, leaving only a narrow gap between the resulting extendedterminals. The 150 μm (6 mil) pitch probe could then be applied to theepoxy terminals. To ensure good contact, the probe was worked back andforth under pressure to maximize the contact to the silver particles.

[0083] The insertion loss was measured for these capacitors over afrequency range from 0 to 10 GHz. Further, other data were taken for theprior art capacitors as described next.

[0084] With respect to the prior art capacitors, these capacitors, amongothers, also were measured from 1 MHz to 1.0 Ghz. The built in modelingcapability of the HP 4291A RF Impedance/Material Analyzer was used tofit a series RLC circuit model to the measured response. The resonantfrequency of the capacitor for the capacitors was determined. As ameasure of the usefulness of the capacitor for decoupling, the range offrequencies over which the capacitor had an impedance lower than 0.3Ωwas obtained and is given in Table 1, below. Value R L C f_(r) f_(l)f_(h) Device nF mΩ pH nF MHz MHz MHZ 1206 100 126 707 74 22  7 70 080510 315 413 8.0 94 — — 0603 10 445 594 8.6 70 — — 0805 2.2 481 568 2.0154 — — 0603 2.2 306 531 1.7 167 — — Murata 10  55 79 6.6 230 75 800 Murata 2.2 133 20 1.4 1000 355  1800  AVX 55 108 30 49 137 11 1500 

[0085] The data reveal the limitations of the prior art capacitorscommonly used for decoupling applications. All of the conventional chipcapacitors exhibit high intrinsic inductance, because of theconfigurations of their plates and terminations. The 0805 and 0603devices tested had high series resistances. If several of them were usedin parallel, as usually is the case, this theoretically would not be aproblem, and they would decouple frequencies higher than the 0.1 μFgenerally used. Of course, multiple 0.1 μF devices can be used in aneffort to “brute force” a low impedance at high frequencies, but on MCMsubstrates, with expensive real estate, multiple capacitors take up alot of room, and it makes more sense to use a small low inductancecapacitor.

[0086] With respect to the Murata devices, these devices have goldterminations on opposite square faces. The manufacturer recommendsattaching one face to a substrate pad with conductive epoxy, andwirebonding the top face to the other substrate terminal. This methoddegrades the performance of these devices by introducing the inductanceof a wirebond. It is possible to mount this device with both terminationfaces vertical, by first using a dot of non-conductive epoxy to tack itdown, and then applying conductive epoxy to the faces of the substratepads. The resulting low inductance connections should give resultssimilar to those achieved for these above measurements, which are betterthan the specifications given by the manufacturer of the devices.

[0087] With respect to the AVX LICA capacitor, it provides substantialcapacitance with extremely low inductance over a fairly wide frequencyrange. However, it is difficult to mount, as its terminals are on thebottom. It was specially designed for IBM to be attached with flip chipsolder bumps. Though versions are available with gold terminations, itis difficult to mount such a capacitor with conductive epoxy withoutshorting.

[0088] In FIG. 7, the results of measurements using the HP 8510B NetworkAnalyzer for certain capacitors are illustrated. These measurements wereperformed in view of the limitations of the HP 4291A in making accuratemeasurements above 1.8 GHz. The range of the HP 4291A only goes to 1.8GHz, and the measurement accuracy decreases substantially above 1 GHz atimpedances less than 1.0Ω.

[0089] Measurements made with one probe were very sensitive to probeforce and wipe. Thus, the capacitors were treated as two-port networks,just like a four-point probe resistance measurement. It can beappreciated that since decoupling capacitors are used to keep the noisefrom one circuit out of other circuits measuring the insertion loss(S₁₂) is appropriate.

[0090] In these latter set of measurements, capacitors were measured byplacing the probes at two locations along the top of the capacitor body,contacting the conductive epoxy. Because of the size difference of thecapacitors, the distance between the probes varied in each case. Eachprobe was applied approximately ¼ of the body width in from the edges.

[0091] It is important to note that the frequency range where thesedevices actually function as capacitors is a small fraction of thefrequency range presented in FIG. 7, except for the capacitor of thepresent invention. Thus, above 1 GHz, the impedance of these capacitorsincreases as the frequency increases, and the capacitors look more andmore like resistors. The AVX LICA capacitor showed the best responsebelow 2 GHz, but again, the response is not flat, and the increasingimpedance effect can be seen to take place from less than 1 GHZ.

[0092] In contrast, the capacitor of the invention exhibits and ischaracterized by an insertion loss of at least −40 db from 1 GHz to atleast 10 GHz. In fact, the graph shows that the capacitor of theinvention exhibited and is characterized by an insertion loss of aboutat least −50 dB over that range. Clearly above 2 GHz, the capacitor ofthe present invention exhibited higher insertion loss than the prior artcapacitors. Because of the novel combination of the present capacitor,no inductive resonance is observed. Instead, at high frequencies, theimpedance is dominated by the resistive component of the R-L-C seriesequivalent circuit. This low resistance can be minimized by usingappropriate metal thicknesses for the floating plate electrode and thetwo patterned plate electrodes, and by adjusting the geometry andconnection points of the patterned plate electrodes in an appropriatemanner. The high insertion loss for the capacitor of the invention isinterpreted as indicating that the capacitor does not exhibit asignificant increase in impedance between 1 GHz and 20 GHz.

[0093] In FIG. 8 there are illustrated two different insertion losscurves for an 8 nF capacitor (as measured at low frequency, i.e., below1 GHz) embodying principles of the invention. Curves A and B are plotstaken at different measurement connections. Essentially, the pitchbetween the probes for Curve B was greater than that for Curve A (i.e.,the probes were further apart for Curve B) The subject capacitor has atotal area of 2 cm×2 cm. The dielectric layer was made of SiO₂ with adielectric constant of Er=3.9. The plates were 1 μm thick.

[0094] In FIG. 9, a direct insertion loss comparison between a 35 nFcapacitor embodying principles of the invention and a 55 nF AVXcapacitor is provided. The capacitor of the invention had an area of 2cm×2 cm. As can be seen, the capacitor embodying principles of theinvention exhibited no inductive resonances.

[0095] Again, the curves for the capacitors embodying principles of theinvention in FIGS. 8 and 9 indicate that the capacitors do not exhibitany significant increase in impedance between 1 GHz and 10 GHz.

[0096] It can be appreciated that modifications and changes to theforegoing embodiments may be possible without departing from the spiritand scope of the invention. It is intended that such modifications andchanges be encompassed by the following claims.

In the claims:
 1. A capacitor which exhibits no significant increase inimpedance at frequencies from 1 GHz to 10 GHz.
 2. The capacitor of claim1 being configured to exhibit an average insertion loss of at least −40dB at frequencies above 1 GHz.
 3. The capacitor of claim 2 beingeffective to exhibit an insertion loss of at least −50 dB at frequenciesfrom 1 to about 10 GHz.
 4. The capacitor of claim 1 comprising afloating plate electrode, at least twoipatterned, plate electrodesoverlying the floating plate electrode, and a dielectric layertherebetween.
 5. The capacitor of claim 4, wherein the floating plateelectrode consists of a metal film with a thickness of about 1000 Å toabout 2 μm.
 6. The capacitor of claim 4, wherein the floating plateelectrode comprises a metal selected from the group consisting ofaluminum and titanium/copper alloy.
 7. The capacitor of claim 4, whereinthe dielectric layer is selected from the group consisting of bariumtitanate, tantalum oxide, aluminum oxide, organic dielectrics andinorganic dielectrics.
 8. The capacitor of claim 4, wherein thedielectric layer is from about 2000 Å to about 1 μm thick.
 9. Thecapacitor of claim 4, wherein the at least two patterned plateelectrodes are selected from the group consisting of metals, conductiveinks and conductive pastes.
 10. The capacitor of claim 4, wherein the atleast two patterned plate electrodes comprise electroforms.
 11. Thecapacitor of claim 4 further comprising an insulating layer on a face ofthe floating plate electrode opposite the at least two patterned plateelectrodes.
 12. The capacitor of claim 11, wherein the insulatingsubstrate is selected from the group consisting of oxidized metal,ceramic, silicon, glass and polymer.
 13. A method of forming a capacitorcomprising the steps of a) providing a metallic layer; b) providing adielectric layer on one face of the metallic layer; and c) providing atleast one pair of patterned electrodes on the dielectric layer on a faceof the dielectric layer opposite the metallic layer.
 14. The method ofclaim 13 further comprising the step of providing an insulating layer ona face of the metallic layer opposite the dielectric layer.
 15. Themethod of claim 14, wherein the step of providing the insulating layercomprises oxidizing one side of the metallic layer until a sufficientlyelectrically insulating layer is formed.
 16. The method of claim 13,wherein the metallic layer is selected from the group consisting ofaluminum or titanium/copper alloy.
 17. The method of claim 13, whereinthe metallic layer is a sheet of aluminum foil.
 18. The method of claim13, wherein the dielectric layer is selected from the group consistingof barium titanate, tantalum oxide, aluminum oxide, an organicdielectric or an inorganic dielectric.
 19. The method of claim 13,wherein the step of providing the patterned plates comprises sputteringa photolithographically defined metal onto the dielectric layer.
 20. Themethod of claim 13, wherein the step of providing the patterned plateelectrodes comprises screen printing a conductive ink or paste onto thedielectric layer.
 21. The method of claim 13, wherein the step ofproviding the metallic layer comprises providing a rollform metallicmaterial.
 22. The method of claim 21, comprising the further step ofproviding an insulating layer by applying an insulating layer to therollform metallic material by lamination.
 23. The method of claim 21,wherein the step of providing an insulating layer by applying aninsulating layer to the rollform metallic material by oxidation.
 24. Themethod of claim 13, wherein a polymer sheet is coated with a metalliclayer to provide an insulating layer and the metallic layer,respectively.
 25. An integrated circuit package comprising a capacitoras set forth in any of claims 1-12.
 26. A decoupling capacitor effectiveto exhibit an insertion loss of at least −40 dB from about 1 GHz toabout 10 GHz, comprising a floating plate electrode, at least twopatterned plate electrodes overlying the floating plate electrode, and adielectric layer therebetween.
 27. A decoupling capacitor as set forthin claim 26, wherein an insulating layer is provided on a face of thefloating plate electrode opposite the dielectric layer.
 28. A decouplingcapacitor as set forth in claim 27, wherein the insulating layer isselected from the group consisting of ceramic, silicon, glass andpolymer.
 29. A decoupling capacitor as set forth in claim 26, whereinthe floating plate electrode has a thickness of about 1000Å to 2 μm. 30.The decoupling, capacitor of claim 26, wherein the dielectric layer isselected from the group consisting of barium titanate, tantalum oxide,aluminum oxide, organic dielectrics,and inorganic dielectrics.
 31. Thedecoupling capacitor of claim 26, wherein the dielectric layer is fromabout 2000Å to about 1 μm thick.
 32. The decoupling capacitor of claim26, wherein the at least two patterned plate electrodes are selectedfrom the group consisting of metals, conductive inks, conductive pastesand electroforms.
 33. A method of forming a capacitor effective toexhibit no significant increase in impedance from about 1 GHz to about10 GHz, comprising the steps of: a) providing a metallic layer on oneside of which is provided an insulating layer; b) providing a dielectriclayer on a side of the metallic layer opposite the insulating layer; andc) providing at least one pair of patterned electrode son the dielectriclayer on a side of the dielectric layer opposite the metallic layer. 34.The method of claim 33 further comprising the step of providing aninsulating layer on a face of the metallic layer opposite the dielectriclayer.
 35. The method of claim 34, wherein the step of providing theinsulating layer comprises oxidizing one side of the metallic layeruntil a sufficiently electrically insulating layer is formed.
 36. Themethod of claim 33, wherein the metallic layer is selected from thegroup consisting of aluminum or titanium/copper alloy.
 37. The method ofclaim 33, wherein the metallic layer is a sheet of aluminum foil. 38.The method of claim 33, wherein the dielectric layer is selected fromthe group consisting of barium titanate, tantalum oxide, aluminum oxide,an organic dielectric or an inorganic dielectric.
 39. The method ofclaim 33, wherein the step of providing the patterned plates comprisessputtering a photolithographically defined metal onto the dielectriclayer.
 40. The method of claim 33, wherein the step of providing thepatterned plate electrodes comprises screen printing a conductive ink orpaste onto the dielectric layer.
 41. The method of claim 33, wherein thestep of providing the metallic layer comprises providing a rollformmetallic material.
 42. The method of claim 41, comprising the furtherstep of providing an insulating layer by applying an insulating layer tothe rollform metallic material by lamination.
 43. The method of claim41, wherein the step of providing an insulating layer by applying aninsulating layer to the rollform metallic material by oxidation.
 44. Themethod of claim 33, wherein a polymer sheet is coated with a metalliclayer to provide an insulating layer and the metallic layer,respectively.
 45. A device comprising power and ground planes, and adiscrete decoupling capacitor effective to decouple current atfrequencies above 2 GHz, said capacitor comprising a floating plate, atleast two patterned electrodes positioned overlying the floating plate,and a dielectric layer between the floating plate and the patternedelectrodes, all electrical attachments to the capacitor being attachedto the patterned electrodes.
 46. The device of claim 45, wherein aninsulating layer is provided on one face of the floating plate electrodeopposite the dielectric layer.
 47. The device of claim 45, wherein theinsulating layer is selected from the group consisting of ceramic,silicon, glass and polymer.
 48. The device of claim 45, wherein thefloating plate electrode has a thickness of about 1000Å to 2 μm.
 49. Thedevice of claim 45, wherein the dielectric layer is selected from thegroup consisting of barium titanate, tantalum oxide, aluminum oxide,organic dielectrics and inorganic dielectrics.
 50. The device of claim45, wherein the dielectric layer of the capacitor is from about 2000Å toabout 1 μm thick.
 51. The device of claim 45, wherein the at least twopatterned plate electrodes of the capacitor are selected from the groupconsisting of metals, conductive inks, conductive pastes andelectroforms.
 52. The device of claim 45, wherein the metallic layer ofthe capacitor is made of a metal selected from the group consisting ofaluminum and Ti—Cu alloy.
 53. A method of forming a capacitor comprisingthe steps of: (a) providing a sheet of metallic material effective toprovide a floating plate electrode; (b) forming a dielectric layer onone side of the metallic sheet; (c) providing at least one pair ofpatterned electrodes on the dielectric layer on a side of the dielectriclayer opposite the metallic sheet; and (d) excising an area of theresulting structure encompassing the patterned plates.
 54. The method ofclaim 53, wherein the step of excising comprises die cutting the subjectarea from the resulting structure.
 55. The method of claim 53, whereinthe step of excising comprises dicing the subject area from theresulting structure.
 56. The method of claim 53, wherein the step ofexcising comprises sawing the subject area from the resulting structure.57. The method of claim 53, comprising the further step of formingterminal pads on the patterned plate electrodes.
 58. The method of claim57, comprising the further step of overcoating the plate electrode,excluding the area occupied by the terminals, with an insulating layer.59. A method of forming a capacitor comprising: (a) providing a sheet ofinsulating material; (b) depositing a metallic layer on one face of theinsulating layer; (c) forming a dielectric layer on the metallic layer;(d) forming a least one pair of patterned plate electrodes on thedielectric layer; and (e) excising an area of the resultant structureencompassing the patterned plate electrodes.
 60. The method of claim 59,wherein the step of excising comprises die cutting the subject area fromthe resulting structure.
 61. The method of claim 59, wherein the step ofexcising comprises dicing the subject area from the resulting structure.62. The method of claim 59, wherein the step of excising comprisessawing the subject area from the resulting structure.
 63. The method ofclaim 59, comprising the further step of forming terminal pads on thepatterned plate electrodes.
 64. The method of claim 63, comprising thefurther step of overcoating the plate electrode, excluding the areaoccupied by the terminals, with an insulating layer.